1. Field
Implementations described herein generally relate to methods and systems for forming dielectric films in high aspect ratio features.
2. Description of the Related Art
Electronic circuits, such as, for example, integrated, display, memory, power, and photovoltaic circuits, are being developed with active and passive features which are ever smaller. Three-dimensional (3D) structures of electronic circuits are formed by vertically stacking a plurality of substrates, which each have features thereon, in a multilayer stacked structure. The features of the different substrates are connected to one another with conventional wire bonds located outside the perimeter edges of the substrates. However, the resultant 3D circuit structures cover larger areas because the wire bonds extend outside the stacked substrates, increasing the circuit size and reducing the areal density of the circuit.
Through-silicon vias (TSV) are being used to electrically connect features of circuits in vertically disposed layers to provide 3D circuit structures having higher areal densities and which are absent side wires. In TSV fabrication, vias are etched in a silicon-containing substrate, such as a silicon wafer or glass panel with a silicon layer, which can already have prefabricated circuits. The etched vias are filled with an electrical conductor, e.g., a metallic conductor comprising a metal such as copper (Cu), silver (Ag), gold (Au), tungsten (W), and solder; or doped semiconductors, e.g., polysilicon. Dielectric layers such as silicon oxide and silicon nitride layers are also typically used to line the walls of the vias before depositing the metallic conductor therein to serve as diffusion barriers, hermetic seals, and other insulating, diffusion barrier or permeation-reducing layers. Multiple substrates are then stacked and vertical electrical connections are formed by the TSVs to connect overlying or underlying features and portions of the resultant three-dimensional circuit. These 3D structures are commonly known as 3D packages, System in Package, or Chip Stack MCM. TSVs allow increased functionality in a smaller areal “footprint” and can also provide faster operating speeds by substantially shortening the electrical paths between the vertically stacked, overlying circuits, as compared with wire bonding methods.
Currently, hermetic cap layers often suffer from low step coverage inside high aspect ratio vias and the film stack inside high aspect ratio vias still suffers from high leakage current and low reliability.
Thus, there remains a need for dielectric deposition methods and systems that can deposit hermetic cap layers with improved step coverage in high aspect ratio features.